Computer basics and the CPU

1. The Von Neumann Architectural Model#

Modern general-purpose digital computers are built upon the foundational Von Neumann architecture, formulated by mathematician and physicist John von Neumann in 1945.

Before this model, early computing machines (such as ENIAC) were hardwired or manually re-cabled to perform specific mathematical calculations. The revolutionary insight of the Von Neumann model was the stored-program concept: both program instructions (code) and the data operated upon reside together in the same addressable electronic memory.

       +-------------------------------------------------------+
       |             CENTRAL PROCESSING UNIT (CPU)             |
       |  +------------------------+  +---------------------+  |
       |  |      Control Unit      |  | Arithmetic & Logic  |  |
       |  |          (CU)          |  |     Unit (ALU)      |  |
       |  +------------------------+  +---------------------+  |
       |  +-------------------------------------------------+  |
       |  |            Internal Registers & Cache           |  |
       |  +-------------------------------------------------+  |
       +---------------------------+---------------------------+
                                   | System Bus
       +---------------------------+---------------------------+
       |               PRIMARY MEMORY (RAM)                    |
       |       [Instructions / Machine Code]  [Active Data]    |
       +---------------------------+---------------------------+
                                   | System Bus
                 +-----------------+-----------------+
                 |                                   |
       +---------v---------+               +---------v---------+
       |   INPUT DEVICES   |               |  OUTPUT DEVICES   |
       | (Keyboard, Mouse) |               |  (Display, Audio) |
       +-------------------+               +-------------------+

The Primary Subsystems

1. Central Processing Unit (CPU): The primary computational engine responsible for interpreting and executing instructions.
2. Primary Memory (RAM): Linear, byte-addressable volatile memory storing active software routines and runtime data.
3. Buses (Control, Address, Data): Parallel physical signal lines interconnecting system components:
   • Control Bus: Transmits timing pulses and read/write synchronization signals.
   • Address Bus: Unidirectional pathway carrying physical memory addresses from CPU to memory.
   • Data Bus: Bidirectional pathway carrying actual instructions and numerical values.
4. Input and Output Interfaces: Bridges converting external analog signals or user interactions into digital binary words and vice versa.

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2. Anatomy of the Central Processing Unit#

The CPU contains several distinct specialized operational units etched into a single microscopic silicon die:

The Control Unit (CU)

The Control Unit serves as the supervisor or conductor of the processor. It does not carry out numerical calculations; instead, it:

• Generates electrical timing and control signals synchronized with the processor's master quartz clock.
• Directs the movement of binary words between memory, registers, and computational units.
• Decodes machine language opcodes into low-level micro-operations.

The Arithmetic Logic Unit (ALU)

The Arithmetic Logic Unit contains combinatorial logic gates that execute all fundamental operations:

• Arithmetic Operations: Binary addition, subtraction, multiplication, and division.
• Logical Operations: Boolean evaluations including AND, OR, NOT, and XOR.
• Bitwise Shifts: Shifting bits left or right for rapid arithmetic scaling and bitmask manipulations.

Specialized Internal Registers

Registers are tiny, ultra-high-speed storage cells constructed from flip-flops directly adjacent to the ALU:

• Program Counter (PC): Holds the physical memory address of the next instruction waiting to be fetched.
• Memory Address Register (MAR): Holds the memory address currently being read from or written to.
• Memory Data Register (MDR): Holds the actual binary data or instruction fetched from, or destined for, RAM.
• Instruction Register (IR): Holds the current machine instruction while the CU decodes it.
• Accumulator (ACC): Temporarily stores intermediate results generated by the ALU.

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3. The Fetch-Decode-Execute (FDX) Machine Cycle#

Every piece of software running on a computer—from an operating system kernel to a web browser—executes as a repetitive sequential cycle called the Instruction Cycle:

        +----------------------------------------+
        |                 FETCH                  |
        |  Read instruction from RAM into CPU;   |
        |  Increment Program Counter (PC).       |
        +-------------------+--------------------+
                            |
                            v
        +----------------------------------------+
        |                 DECODE                 |
        |  Control Unit parses opcode & operands |
        |  identifying required data pathways.   |
        +-------------------+--------------------+
                            |
                            v
        +----------------------------------------+
        |                EXECUTE                 |
        |  ALU computes operation, moves data,   |
        |  or updates status flags.              |
        +-------------------+--------------------+
                            |
                            v
        +----------------------------------------+
        |                 STORE                  |
        |  Write result to Accumulator or RAM.   |
        +-------------------+--------------------+
                            |
                            +---> [ Repeat for Next Instruction ]

Detailed Execution Trace

Suppose a program needs to execute: ADD 5 to the current value in Memory Location 0x0100.

1. Fetch:
   • The CPU copies the address in the PC (e.g., 0x00A0) into the MAR.
   • The Control Unit pulses the read wire on the control bus.
   • The memory controller places the machine code instruction located at 0x00A0 onto the data bus into the MDR.
   • The instruction moves from MDR to the IR.
   • The PC automatically increments to 0x00A1 to point to the subsequent instruction.
2. Decode:
   • The Control Unit decodes the opcode in the IR, identifying an ADD operation requiring an operand stored at 0x0100.
3. Execute:
   • The data at address 0x0100 is fetched into the ALU.
   • The ALU adds the value to the accumulator register.
4. Store / Writeback:
   • The result is latched into the accumulator, and the cycle begins anew for the instruction at 0x00A1.

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4. The Memory Hierarchy: Balancing Speed and Capacity#

Processors operate at nanosecond timescales, whereas secondary disks operate hundreds or thousands of times slower. Computer engineers resolve this mismatch through a layered memory hierarchy:

| Hierarchy Level | Typical Access Latency | Typical Capacity | Volatility | Primary Purpose | | :--- | :--- | :--- | :--- | :--- | | CPU Registers | $< 1\text{ ns}$ ($0.5 - 1$ cycle) | $64 - 2048\text{ bytes}$ | Volatile | Immediate ALU operand staging | | L1 Cache | $1 - 2\text{ ns}$ ($3 - 4$ cycles) | $32 - 128\text{ KB}$ per core | Volatile | Most critical active instructions/data | | L2 Cache | $3 - 5\text{ ns}$ ($10 - 15$ cycles) | $512\text{ KB} - 2\text{ MB}$ per core | Volatile | High-priority working set buffer | | L3 Cache | $10 - 20\text{ ns}$ ($40 - 60$ cycles) | $8 - 64\text{ MB}$ shared | Volatile | Shared inter-core data cache | | Main Memory (RAM) | $50 - 80\text{ ns}$ | $8 - 128\text{ GB}$ | Volatile | Active operating system and running apps | | Solid-State Drive (SSD)| $20 - 100\ \mu\text{s}$ | $256\text{ GB} - 4\text{ TB}$ | Non-volatile | Persistent files, programs, OS image | | Hard Disk Drive (HDD) | $5 - 10\text{ ms}$ ($5,000,000\text{ ns}$)| $1 - 20\text{ TB}$ | Non-volatile | Long-term mass data archiving |

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The Principle of Locality: Caching works because software demonstrates temporal locality (memory accessed recently will likely be accessed again soon) and spatial locality (memory near recently accessed addresses will likely be needed next).

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5. Performance Factors: Beyond Clock Speed#

A widespread consumer misconception is that clock speed (measured in gigahertz, $\text{GHz}$) provides a complete measurement of processor capability. This is known in computing history as the Megahertz Myth.

$$\text{Processor Performance} = \text{Clock Frequency} \times \text{Instructions Per Cycle (IPC)}$$

Key Determinants of Real-World Computing Speed

1. Instructions Per Cycle (IPC): How many instructions a microarchitecture can complete during one single clock tick, driven by pipelining and branch prediction.
2. Multi-Core Architecture: Multiple independent execution cores on one chip. While a single core can execute one instruction stream, four cores can theoretically process four distinct threads simultaneously.
   • Amdahl's Law: The speedup of a multi-core processor is limited by the serial (non-parallelizable) portion of the software.
3. Cache Size and Memory Bandwidth: A processor with massive L3 cache spends significantly less time stalled waiting for high-latency RAM requests.
4. Thermal Throttling: When a CPU reaches high temperatures, internal safety circuits lower the clock frequency to avoid permanent hardware damage.

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6. Common Misconceptions to Avoid#

• Misconception 1: The CPU is the entire desktop computer. Correction: The CPU is merely the silicon processor chip plugged into the motherboard. The computer includes memory, motherboard, power supply, and storage drives.
• Misconception 2: Doubling CPU cores doubles speed for all applications. Correction: An application must be written with multi-threading support to utilize multiple cores. Single-threaded tasks run on only one core, leaving others idle.
• Misconception 3: RAM stores files when the computer is turned off. Correction: RAM is volatile memory; when power cuts, its contents are cleared immediately. Files are permanently retained on non-volatile SSD or HDD storage.
• Misconception 4: 64-bit means twice as fast as 32-bit. Correction: 64-bit refers to the width of the CPU registers and memory address bus. Its primary advantage is enabling the CPU to address more than $4\text{ GB}$ of RAM directly ($2^{64}$ address space vs $2^{32}$).